Back end of line (BEOL) interconnects are typically created using a dual damascene process that involves patterning trenches and vias in a dielectric and then filling these features with a conductor such as copper (Cu). A barrier layer (e.g., tantalum nitride (TaN)) is often employed lining the trenches/vias to prevent Cu diffusion into the dielectric.
However, having a via structure without TaN at the via bottom (or with large contact area at the via bottom) is desirable to reduce via resistance and improve electromigration (EM) performance. However, a barrier etch-back (gouging) process (using for example argon (Ar+) etching in physical vapor deposition (PVD) chamber) causes severe low-κ damage at the trench bottom which leads to an increase in capacitance and reliability degradation.
Alternatively, a conventional wet etching (gouging) process can be employed to increase contact area at the via bottom. However, due to the isotropic nature of a wet etching process, under-cut (lateral etching) of the dielectric occurs, resulting in under-cut areas that are difficult to fill by Cu plating since a seed layer cannot be deposited around under-cut area.
Thus, improved techniques for forming Cu interconnects without a barrier layer at the via bottom would be desirable.